SiLK™ is a trademark of Dow Chemical for a polymer thermoset resin exhibiting very low dielectric constant, useful in semiconductor manufacturing, and described in Balance et al., U.S. Pat. No. 5,523,163, for LOW DIELECTRIC CONSTANT COATINGS, issued Jun. 4, 1996, and Bremmer et al. U.S. Pat. No. 5,906,859, for a METHOD FOR PRODUCING LOW DIELECTRIC COATINGS FROM HYDROGEN SILSEQUIOXANE RESIN, issued May 25, 1999, and Bremmer et al., U.S. Pat. No. 6,210,749, THERMALLY STABLE DIELECTRIC COATINGS, issued Apr. 3, 2001, the disclosures of all of which are incorporated by reference herein in their entirety. SiLK™ structures are increasingly being used to replace silicon oxide (SiO2) as a dielectric because of its superior dielectric qualities, namely a dielectric constant of 2.65 compared with 4.1 for silicon oxide.
SiLK™ also demonstrates comparable toughness and greater resilience than the more brittle silicon oxide. Low dielectric constant in a material permits smaller structures to be manufactured, which in turn permits closer packing of devices, faster speeds, and reduced crosstalk. The spin-on aromatic polymer has no fluorine in its composition, delivers superior planarization and gapfill, and is stable to 490° C. These properties have made SiLK™ popular for a variety of CMOS technologies demanding “low-K” interlayer dielectrics, such as copper/damascene and aluminum/tungsten technologies.
There are stress problems, however, in vias built with SiLK™ that do not occur with traditional silicon oxide vias. These stresses result in thermal cycle and in-line via-resistance shifts. There are at least three cases in which two-dimensional modeling has predicted high stresses in SiLK™ vias wherein thermal-cycle reliability failures have been directly correlated with the stress, namely (1) vias built in SiLK™ rather than silicon oxide, (2) vias built in SiLK™ wherein the subsequent level is executed in silicon oxide instead of SiLK™ and (3) vias built in SiLK™ wherein the next level is built in oxide compared with vias built in SiLK™ with a stress-relief layer prior to the subsequent level being built in oxide.
A stress problem with SiLK™ is illustrated in FIG. 1a, showing a pair of semiconductor cross-sections depicting a typical prior art oxide embodiment A and a prior art SiLK™ embodiment B of a wafer structure, each comprising a base layer 1 of silicon substrate, atop of which is a silicon oxide base layer 2. Upon these are a first conductive line 3 and a second conductive line 4, usually made of copper metal, that join one another through a first via 5, which penetrates a level-separating nitride layer 6 that separates the first level 10 from a second level 20. In both drawings, third 30 and fourth 40 levels are shown, also separated by level-separating nitride layers 6, the third level 30 comprising a silicon oxide layer 8 and the fourth level 40 comprising a silicon oxide layer 9 beneath a silicon nitride cap 11. Cross-section A shows a typical via 5 defined by a first level silicon oxide layer 7 and partly by the base silicon oxide layer 2. Cross-section B, however, shows a via 5 defined by a second level SiLK™ layer 7′ and a base level SiLK™ structure 2′. The differences between the two structures may be seen in corresponding stress analysis images A′, B′, wherein darkened areas indicate high stresses. Comparing B′ to A′, it is apparent that the SiLK™ via structure creates much more stress and distortion than the traditional silicon oxide structure.
Referring to FIG. 1b, plots 100 of via resistance shift in Ohms/link are shown for SiLK™ and for oxide, respectively. What is needed is a method suitable for making SiLK™ via structures with reduced stress.